Liquid crystal display is currently a common flat display device, wherein Thin Film Transistor Liquid Crystal Display (abbreviated as TFT-LCD) is a mainstream product for the liquid crystal display.
Advanced Super Dimension Switch (referred to as AD-SDS, abbreviated as ADS) based TFT-LCD becomes widely used due to its characters of low power consumption, wide viewing angle and the like. ADS technology forms a multi-dimensional electric field mainly through an electric field generated by fringes of a slit electrode within a same plane and an electric field generated between a slit electrode layer and a plate-shaped electrode layer so that liquid crystal molecules in all orientations between the slit electrodes and directly above the electrodes in a liquid crystal cell can be rotated, thus a work efficiency of the liquid crystal may be improved and the light transmission efficiency may be increased. The AD-SDS technology can improve the image quality of the TFT-LCD products, and has advantages of high resolution, high transmittance, wide viewing angle, high aspect ratio, low chromatic aberration, being free of push Mura and the like.
As a common electrode is also formed on an ASD type TFT-LCD array substrate, there is a need for an additional patterning process to form the common electrode in the process for fabricating the ASD type TFT-LCD array substrate.
Currently, there generally need several patterning processes during the fabrication of the ASD type TFT-LCD array substrate, and each patterning process further comprises a film forming process, an exposing process, a developing process, an etching process and a stripping process and the like, respectively. Therefore, to reduce the time for patterning processes means that the fabrication cost can be reduced.
A method for fabricating ASD type TFT-LCD array substrate through six patterning processes is disclosed in the prior art (shown in FIG. 1), the method comprises:
Step 1, depositing a first metal film, to form gate lines, a gate electrode 11 and a common electrode 12 by a first patterning process.
Step 2, depositing a first insulating film, a semiconductor film, a doped semiconductor film, to form a gate insulating layer 13, a semiconductor active layer 14 (composed of semiconductor layer and semiconductor doped layer) by a second patterning process.
Step 3, depositing a first transparent conductive film, to form a plate-shape pixel electrode 14′ by a third patterning process.
Step 4, depositing a second metal film, to form a source electrode 16, a drain electrode 17 and data lines by a fourth patterning process.
Step 5, depositing a second insulating film to form a passivation layer 18, forming a through hole passing through the passivation layer 18 and the gate insulating layer 13 by a fifth patterning process, to expose common electrode lines 12.
Step 6, depositing a second transparent conductive film, to form a common electrode 19 having slit by a six patterning process, the common electrode 19 is electrically connected to the common electrode lines 12 via the through hole formed in step 5.
Such method needs six patterning processes, and the fabrication cost is still high. In order to enhance market competitiveness, improve market share, there is a need for further decreasing times of the patterning processes during the fabrication of the array substrate.